Given today's high clock rates and transmission line effects when signals must travel between integrated circuit chips, changes along signal paths can occur over time that affect signal timing. As a system heats and cools during operation, and/or develops hot and cool spots, the skew between data bits, or between data bits and strobe signals can likewise change as data bit signals and strobe signals travel off chip and between chips through various system-level paths. Therefore, it would be useful to have a way to perform dynamic timing calibration and re-calibration from time to time during system operation, and to do so quickly and dynamically without affecting the normal operation of the system.
One application where such a continuously adaptive calibration or training mechanism for data interface timing calibration is especially useful is to compensate for variable system-level delays in dynamic memory interfaces where DQ data bits can develop a skew problem with respect to the DQS strobe used to sample them, or where the optimal DQS strobe timing over all data bits varies during the functional operation of the system. Similarly, at the timing interface between the Phy and internal core clock domains in a dynamic memory based controller system, the timing relationship between an internal capture clock and data coming from the Phy can also drift due to system-level delays. In addition, jitter can develop between data bits and strobes, or between signals in different clock domains, and it would also be useful to resolve jitter issues while performing a continuous timing calibration function.